1. Field of the Invention
The present invention relates to nonvolatile semiconductor memories for trimming voltages by a built-in self-test (BIST).
2. Background Art
In nonvolatile semiconductor memories, control voltages including a reference voltage, a reading voltage, and a writing voltage vary greatly among chips. It is therefore necessary to adjust these voltages to a target voltage before shipment.
Conventionally, in order to shorten a time of adjustment and so on, test circuits are included in chips. A tester inputs commands to the test circuits, so that such a kind of test can be automatically conducted by a nonvolatile semiconductor memory.
In some conventional methods of adjusting a reference voltage, a target voltage is inputted to the test circuits from the outside and the target voltage is compared with a voltage corresponding to an internal parameter (for example, see Japanese Patent Laid-Open Publication No. 2001-255948).
In the prior art, in the case of successful adjustment, the test circuit sets a completed flag (outputs a trimming flag signal) to terminate the adjustment.
On the other hand, in the case of unsuccessful adjustment, the test circuit increases (or reduces) the voltage corresponding to the parameter, so that the reference voltage and so on is adjusted to a value close to the external target voltage.
In the prior art, there is a problem that when the trimming flag signal has noise at the examination of the adjustment, control voltages are shifted away from the target voltage and thus desired control voltages cannot be obtained.